Improving Instruction Delivery with a Block-Aware ISA
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چکیده
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and bandwidth are limited by instruction cache misses, multi-cycle instruction cache accesses, and target or direction mispredictions for control-flow operations. This paper introduces a block-aware ISA (BLISS) that helps accurate instruction delivery by defining basic block descriptors in addition to and separate from the actual instructions in a program. We show that BLISS allows for a decoupled front-end that tolerates cache latency and allows for higher speculation accuracy. This translates to a 20% IPC and 14% energy improvements over conventional front-ends. We also demonstrate that a BLISS-based front-end outperforms by 13% decoupled front-ends that detect fetched blocks dynamically in hardware, without any information from the ISA.
منابع مشابه
Block-aware Instruction Set Architecture a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
This dissertation examines the use of a block-aware instruction set architecture (BLISS) to address the front-end challenges of modern processors. The theme of BLISS is to allow software to assist the front-end hardware by providing architecture support for control-flow prediction and instruction delivery. BLISS defines basic block descriptors in addition to and separately from the actual instr...
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تاریخ انتشار 2005